A chip that includes a memory, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), or a synchronous dynamic random access memory (SDRAM), typically uses a system clock to generate signals for allowing memory accesses, including read and write functions. Rising and/or falling edges of the system clock signal are used to trigger the strobe inputs.
In such memories with multiple strobe inputs, read or write memory operations may occur at a rising edge of any strobe signal. One way to generate two strobes is to use the system clock to generate the first strobe signal and an inversion of the system clock to generate the second strobe signal. This introduces a requirement to maintain a duty cycle for memory functions that does not substantially deviate from 50% of the clock cycle, in order to optimize memory access bandwidth.
A precise 50% duty cycle is often difficult to achieve or maintain, particularly as the complexity of an integrated circuit (IC) increases. With the increasing functionality of modern electronic devices, there are corresponding increases in the demands being placed on memory bandwidth. An economical solution for increasing memory bandwidth would therefore be beneficial, particularly where such a solution could be adapted for existing memory devices.